1. Field of the Invention
This invention relates generally to semiconductor memory modules and, more particularly, to multi-level packages wherein an upper and at least one lower level DRAM integrated circuit packages are stacked one over the other by which to assemble a high density, low profile, three-dimensional memory module.
2. Background Art
A conventional memory module for dynamic random access memory (DRAM) semi-conductor integrated circuits typically includes a printed wiring board (PWB) substrate card and a number of DRAM integrated circuit (IC) packages mounted to the PWB card by means of surface mount technology. Running along one edge of the PWB card is a row of gold plated metallic contact pads or fingers to be inserted into a connector socket that is mounted at a mother board. These multi-package modules are generally referred to as either a single in-line memory module (SIMM) or a dual in-line memory module (DIMM), depending upon whether the gold finger contacts on the PWB card edge are isolated or interconnected to the packages on both sides of the card by way of through holes. Typically, a single row of DRAM packages numbering from four to nine is mounted on one side of the module. Both sides of a single SIMM or DIMM module can be populated to increase the number of integrated circuit packages on board. This is often referred to as a normal or monolithic assembly of memory modules. The number of packages that can be mounted is limited by the size of the SIMM or DIMM modules that are regulated by internationally accepted standards.
The internal content of the DRAM memory density, commonly measured in terms of megabits, plus the number of the packages assembled per memory module determines the total module density, measured in megabytes. Hence, a DIMM module containing eight 128 Mb DRAM packages produces a module with 128 MB of memory density.
It is often desirable to increase the memory densities within the given space on a single DIMM. The usual monolithic assembly of packages to fabricate a memory module is limited by the space that is available to mount the DRAM packages. For a standard DIMM module populated on both sides of the PWB card, the typical number of DRAM packages is 18, by using lead frame packages such as thin small outline packages (TSOP) or even smaller sized chip scale packages (CSP) and fine pitch ball grid array (FBGA) packages. To double the memory density within a given DIMM module, the usual solution has been to use pre-stacked DRAM packages. In order to solder the leads of the top and bottom stacked packages together, an intermediate medium, or interposer, is often used. This interposer needs to contain simple circuitry to reroute the chip select function of the top package to the interconnecting pads on the PWB card, because the upper and lower packages are overlapping in the space originally intended for just a single package.
As a result of the foregoing, separate chip select signal traces are needed to identify the top DRAM package and distinguish it from the bottom package. An additional and separate assembly process is required to first join the leads of the upper package to the lower package. Furthermore, after the stacking assembly is completed, each pair of stacked DRAMs, must be electrically tested again and visually inspected to ensure that the stacked arrangement is functional.
When assembled to the DIMM module cards, the stacked packages can achieve the goal of doubling the amount of the memory density. However, depending upon the shape and location of the leads which join the top and the bottom packages, the pair of packages that are stacked one above the other often presents problems to assembly machines, such as a chip placement machine, by confusing its vision system for checking the lead pattern. What is even more, once the stacked package is assembled, in the situation where one of the two stacked packages is not functioning correctly and is in need of repair, the entire stacked package must be removed from the DIMM module and replaced. Therefore, even though only one of the two packages in the stacked pair of packages is malfunctioning, the other properly functioning package must nevertheless be sacrificed.
Accordingly, what is needed is an efficient means for doubling the memory density in a memory module which avoids the disadvantages described above while minimizing the assembly cost, reducing assembly time, and avoiding additional waste and inefficiency that is incurred during testing and repair.
Examples of stacked semiconductor integrated circuits mounted on a substrate are available by referring to the following United States patents:
In general terms, multi-level packages comprising dynamic random access memory (DRAM) semi-conductor integrated circuit (IC) devices are surface mounted to one or both sides of a printed wiring board substrate in order to manufacture a high density, low profile, three dimensional memory module (e.g. either a single in-line or a dual in-line memory module). Each multi-level package includes different upper and lower level DRAM IC packages that are efficiently stacked one above the other so as to occupy no more space on the board than that normally occupied by a single upper level IC package. In a preferred embodiment, the upper level IC package of each stacked package is a lead frame package, such as a thin small outline package (TSOP), and the lower level package is a chip scale package (CSP). The leads of the upper level (TSOP) package are of sufficient length so that the standoff height of the upper level package is taller than a standard package so as to provide a sufficient clearance thereunder in which to receive at least one lower level (CSP) package. In this same regard, the lower level (CSP) package is a leadless device that is characterized by a smaller footprint and profile than the corresponding footprint and profile of the upper level package.
The leadless lower level IC package of the stacked pair of packages is electrically connected to the printed wiring board substrate by means of solder balls and surface contact bonding pads. The upper level IC package is connected to the printed wiring board substrate by means of its relatively long leads and surface contact bonding pads. At least some pairs of the bonding pads associated with each of the upper and lower level IC packages are interconnected with one another either along the surface of the substrate or at interior layers thereof so as to be capable of sharing the same signal traces, whereby the bonding pads of the upper and lower packages can be connected in electrical common on a memory module. Because the upper and lower level packages are physically isolated, there is no need for an intermediate interposer, common to pre-stacked packaging, to reroute the chip select pin. Thus, the necessity for adding an interposer between the upper and lower level IC packages is avoided so that the total number of stacked packages that can be assembled for manufacturing a standard monolithic memory module can be doubled relative to a conventional memory module without consuming additional space on the substrate.